index of /notes/hw/memory_cache/

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Memory Model and Formalization 07-May-2025
MC-02h - memory constency intro & sequential consistency 06-May-2025
MC-01h - coherence introduction 05-May-2025



Introduction

without further notes, all contents are copy-verbatim or derived from this book:;

A Primer on Memory Consistency and Cache Coherence (2nd Edition), Synthesis Lectures on Computer Architecture, Vijay Nagarajan, Daniel J.Sorin, Mark D.Hill and David A. Wold
https://pages.cs.wisc.edu/~markhill/papers/primer2020_2nd_edition.pdf

this section is under CC-BY-SA-4.0. The above notice must be preserved.


§ consistency and coherence

  • Memory -> Consistency : (memory model), a precise, architecturally visible definition of shared memory correctness; rules about loads and stores and how they act upon memory. Also relaxed (weak) memory model w.r.t. re-ordering.
  • Cache -> Coherence : seems to make caches of a shared-memory system as functionally invisible; it does so by propagating a processor’s write to other processor’s caches

Consistency vs. Coherence
“It is worth stressing that unlike consistency which is an architectural specification that defines shared memory correctness, coherence is a means to supporting a consistency model”

  • The coherence protocol provides the processor core pipeline an abstraction of a memory system. It alone cannot determine memory behaviour
  • A memory consistency implementation can use cache coherence as a “black box”

§ self-test quizs

  • what’s the difference / relationship between memory consistency and cache coherence (or just explain them)
  • what is the fundamental issue that causes the incoherence? (multiple actors with access to caches and memory)
  • (cont.) which actors are there? (processor cores, DMA engines, external devices that can read/write caches and memory)

§ Glossary

  • LLC : last-level cache
  • HLL : high-level language
  • RAS : Raliability (prevent or correct errors), Availability (uptime) and Serviceability (diagnose and repair)

Notes for future readings

  • M. L. Scott. Shared-Memory Synchronization. Synthesis Lectures on Computer Architecture.

  • Lamport, “How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs,” in IEEE Transactions on Computers, vol. C-28, no. 9, pp. 690-691, Sept. 1979, doi: 10.1109/TC.1979.1675439. keywords: {Computer design;concurrent computing;hardware correctness;multiprocessing;parallel processing}
    https://lamport.azurewebsites.net/pubs/lamport-how-to-make.pdf