Notes on cmake & makefile


This is a collection of notes from various sources. I am not the author of any of the following content.




A simple Makefile

    echo "this is a test"

exec make test gets:

echo "this is a test"
this is a test

A general rule:

target: prerequisites
<TAB> recipe



By default, Makefile targets are “file targets” - they are used to build files from other files. Make assumes its target is a file, and this makes writing Makefiles relatively easy:

foo: bar
  create_one_from_the_other foo bar

However, sometimes you want your Makefile to run commands that do not represent physical files in the file system. Good examples for this are the common targets “clean” and “all”. Chances are this isn’t the case, but you may potentially have a file named clean in your main directory. In such a case Make will be confused because by default the clean target would be associated with this file and Make will only run it when the file doesn’t appear to be up-to-date with regards to its dependencies.

These special targets are called phony and you can explicitly tell Make they’re not associated with files, e.g.:

.PHONY: clean
  rm -rf *.o

Now make clean will run as expected even if you do have a file named clean.

In terms of Make, a phony target is simply a target that is always out-of-date, so whenever you ask make <phony_target>, it will run, independent from the state of the file system. Some common make targets that are often phony are: all, install, clean, distclean, TAGS, info, check.


It is a good practice not to call clean in all or put it as the first target. clean should be called manually when cleaning is needed as a first argument to make:

$ make clean
Cleaning up...

Variables and basic gcc compiling

CC = gcc
# This is also called a recursive expanded variable, and it is used in a rule as shown below:

hello: hello.c
    ${CC} hello.c -o hello

use make hello :

gcc hello.c -o hello

Avoiding infinite loop (self-reference)

an example of self-reference:

CC = gcc
CC = ${CC}

    @echo ${CC}

which results in:

Makefile:8: *** Recursive variable 'CC' references itself (eventually).  Stop.

to avoid self-reference, use operator := (simply expanded variable):

CC := gcc
CC := ${CC}

    @echo ${CC}

Patterns and functions

# Usage:
# make        # compile all binary
# make clean  # remove ALL binaries and objects

.PHONY = all clean

CC = gcc                        # compiler to use


SRCS := $(wildcard *.c)
BINS := $(SRCS:%.c=%)

all: ${BINS}

%: %.o
        @echo "Checking.."
        ${CC} ${LINKERFLAG} $< -o $@

%.o: %.c
        @echo "Creating object.."
        ${CC} -c $<

        @echo "Cleaning up..."
        rm -rvf *.o ${BINS}


  • .PHONY explicitly tells make which targets are not real files.
  • LINKERFLAG are used by gcc during compiling. In this case -lm means link math library.
  • wildcard *.c lists out all .c files
  • BINS := $(SRCS:%.c=%) ,This is called as substitution reference. In this case, if SRCS has values 'foo.c bar.c', BINS will have 'foo bar'.
  • all: ${BINS}: The phony target all calls values in ${BINS} as individual targets.
%: %.o
  @echo "Checking.."
  ${CC} ${LINKERFLAG} $< -o $@

Suppose foo is one of the values in ${BINS}. Then % will match foo, ( % can match any target name). Below is the rule in its expanded form:

foo: foo.o
  @echo "Checking.."
  gcc -lm foo.o -o foo


%.o: %.c
  @echo "Creating object.."
  ${CC} -c $<

Every prerequisite in the previous rule is considered a target for this rule. Below is the rule in its expanded form:

foo.o: foo.c
  @echo "Creating object.."
  gcc -c foo.c
  • $< match the given prerequisite and $@ match the target name