Aarch64 exceptions

ESR_EL1 (Exception Syndrome Register (EL1)

bit range is inclusive on both ends
-----------------------------------

BITS[63:37] RES0
BITS[36:32] ISS2    < when FEAT_LS64 implemented
BITS[31:26] EC      Exception Class
BIT [25]    IL      Instruction Length for sync exceptions
                    - 0 : 16bit instruction trapped
                    - 1 : 32bit Instruction trapped
BITS[24:0 ] ISS     Instruction Specific Syndrome

EC in ESR

taken from linux/arch/arm64/include/asm/esr.h

ESR_ELx_EC_UNKNOWN  (0x00)
ESR_ELx_EC_WFx      (0x01)
UNALLOCATED         (0x02)
ESR_ELx_EC_CP15_32  (0x03)
ESR_ELx_EC_CP15_64  (0x04)
ESR_ELx_EC_CP14_MR  (0x05)
ESR_ELx_EC_CP14_LS  (0x06)
ESR_ELx_EC_FP_ASIMD (0x07)
ESR_ELx_EC_CP10_ID  (0x08)  /* EL2 only */
ESR_ELx_EC_PAC      (0x09)  /* EL2 and above */
UNALLOCATED         (0x0A - 0x0B)
ESR_ELx_EC_CP14_64  (0x0C)
ESR_ELx_EC_BTI      (0x0D)
ESR_ELx_EC_ILL      (0x0E)
UNALLOCATED         (0x0F - 0x10)
ESR_ELx_EC_SVC32    (0x11)
ESR_ELx_EC_HVC32    (0x12)  /* EL2 only */
ESR_ELx_EC_SMC32    (0x13)  /* EL2 and above */
UNALLOCATED         (0x14)
ESR_ELx_EC_SVC64    (0x15)
ESR_ELx_EC_HVC64    (0x16)  /* EL2 and above */
ESR_ELx_EC_SMC64    (0x17)  /* EL2 and above */
ESR_ELx_EC_SYS64    (0x18)
ESR_ELx_EC_SVE      (0x19)
ESR_ELx_EC_ERET     (0x1a)  /* EL2 only */
UNALLOCATED         (0x1B)
ESR_ELx_EC_FPAC     (0x1C)  /* EL1 and above */
ESR_ELx_EC_SME      (0x1D)
UNALLOCATED         (0x1E)
ESR_ELx_EC_IMP_DEF  (0x1f)  /* EL3 only */
ESR_ELx_EC_IABT_LOW (0x20)
ESR_ELx_EC_IABT_CUR (0x21)
ESR_ELx_EC_PC_ALIGN (0x22)
UNALLOCATED         (0x23)
ESR_ELx_EC_DABT_LOW (0x24)
ESR_ELx_EC_DABT_CUR (0x25)
ESR_ELx_EC_SP_ALIGN (0x26)
ESR_ELx_EC_MOPS     (0x27)
ESR_ELx_EC_FP_EXC32 (0x28)
UNALLOCATED         (0x29 - 0x2B)
ESR_ELx_EC_FP_EXC64 (0x2C)
UNALLOCATED         (0x2D - 0x2E)
ESR_ELx_EC_SERROR   (0x2F)
ESR_ELx_EC_BREAKPT_LOW  (0x30)
ESR_ELx_EC_BREAKPT_CUR  (0x31)
ESR_ELx_EC_SOFTSTP_LOW  (0x32)
ESR_ELx_EC_SOFTSTP_CUR  (0x33)
ESR_ELx_EC_WATCHPT_LOW  (0x34)
ESR_ELx_EC_WATCHPT_CUR  (0x35)
UNALLOCATED         (0x36 - 0x37)
ESR_ELx_EC_BKPT32   (0x38)
UNALLOCATED         (0x39)
ESR_ELx_EC_VECTOR32 (0x3A)  /* EL2 only */
UNALLOCATED         (0x3B)
ESR_ELx_EC_BRK64    (0x3C)
UNALLOCATED         (0x3D - 0x3F)

ESR_ELx_EC_MAX      (0x3F)
ESR_ELx_EC_SHIFT    (26)
ESR_ELx_EC_WIDTH    (6)
ESR_ELx_EC_MASK     (UL(0x3F) << ESR_ELx_EC_SHIFT)
ESR_ELx_EC(esr)     (((esr) & ESR_ELx_EC_MASK) >> ESR_ELx_EC_SHIFT)

footnotes, licenses

linux/arch/arm64/include/asm/esr.h
--------------------------------------------
SPDX-License-Identifier: GPL-2.0-only

Copyright (C) 2013 - ARM Ltd
Author: Marc Zyngier <marc.zyngier@arm.com>