Aarch64 exception vectors

each vector is aligned to 2^7 ie 0x80 bytes

TABLE_BASE
    CURRENT_EL + SP0    sync    // el1_t
    CURRENT_EL + SP0    irq
    CURRENT_EL + SP0    fiq
    CURRENT_EL + SP0    serror

    CURRENT_EL + SPX    sync    // el1_h
    CURRENT_EL + SPX    irq
    CURRENT_EL + SPX    fiq
    CURRENT_EL + SPX    serror

    LOWWER_EL  +        sync    // aarch64 // el0_
    LOWWER_EL  +        irq     
    LOWWER_EL  +        fiq     
    LOWWER_EL  +        Serror  

    LOWWER_EL  +        sync    // aarch32
    LOWWER_EL  +        irq     
    LOWWER_EL  +        fiq     
    LOWWER_EL  +        Serror